FPGA可编程逻辑器件芯片5SGXEA4K3F35I4N中文规格书

2023年12月20日发(作者：道奇汽车多少钱)

GPIO FunctionalityThe port multiplexing scheme provides best granularity, as every pin can

be controlled on an individual basis. If

SPORT2 is used in any mode that

does not require the secondary transmit data feature, the

PA1 pin can still

be used as GPIO or as

FunctionalityEvery port pin can operate in GPIO mode. This is the default after reset

and is controlled by the port-specific

PORTx_FER function enable register.

Every port has a dedicated set of MMR registers that control GPIO func-tionality. Every bit in these registers represents a certain GPIO pin of the

specific port. Refer to Figure9-2 for a related diagram.?In this chapter, the naming convention for registers and bits uses a

lowercase “x” to represent A through J. For example, the name

PORTx_FER represents

PORTA_FER,

PORTB_FER, and so on, through

PORTJ_FER. The bit name

Px0 represents

PA0,

PB0, and so on,

through

PJ0. This convention is used to discuss registers common

to the ten default, every GPIO is in input mode. The input drivers are not

enabled which avoids the need for unnecessary current sinks and the exter-nal pulling of resistors on unused or do not care pins.

Input ModeThe default mode of every GPIO pin after reset is input mode, but the

input drivers are not enabled. To enable any GPIO input drivers, set the

corresponding bits in the input enable register

PORTx_INEN. When

enabled, a read from the

PORTx register returns the logical state of the

input pin. The input signal does not overwrite the state of the flip-flop

used for the output case. That state can only be altered by software. If the

input driver is enabled, a write to the

PORTx register can alter the state of

the flip-flop, but the change cannot be read -BF54x Blackfin Processor Hardware Reference

Programming Examples CC = bittst(r6, bitpos(RESET_WDOG)); if !CC jump __watchdog_reset;/* optionally, warn at system level or host device here */__watchdog_reset:/* optionally, set NOBOOT bit to avoid reboot in case */ p0.h=hi(SYSCR); p0.l=lo(SYSCR); r0 = w[p0](z); bitset(r0,bitpos(NOBOOT)); w[p0] = r0;/* start watchdog timer, reset if expires */ p0.h = hi(WDOG_CNT); p0.l = lo(WDOG_CNT); r0.h = hi(WDOGPERIOD); r0.l = lo(WDOGPERIOD); [p0] = r0; p0.l = lo(WDOG_CTL); r0.l = WDEN | WDEV_RESET; w[p0] = r0; ... jump _main;_:The subroutine shown in Listing12-2 can be called by software to service

the watchdog. Note that the value written to the

WDOG_STAT register does

not -BF54x Blackfin Processor Hardware Reference