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元器件交易网
HD74LS273
Octal D-type Positive-edge-triggered Flip-Flops (with Clear)
REJ03D0473–0300
Rev.3.00
Jul.15.2005
The HD74LS273, positive-edge-triggered flip-flops utilize LS TTL circuitry to implement D-type flip-flop logic with a
direct clear input.
Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going
edge of the clock pulse.
When the clock input is at either the high or low level, the D input signal has no effect at the output.
Features
? Ordering Information
Part Name Package Type
Package Code
(Previous Code)
PRDP0020AC-B
(DP-20NEV)
PRSP0020DD-B
(FP-20DAV)
Package
Abbreviation
Taping Abbreviation
(Quantity)
HD74LS273P DILP-20 pin
HD74LS273FPEL SOP-20 pin (JEITA)
HD74LS273RPEL SOP-20 pin (JEDEC)
P —
FP EL (2,000 pcs/reel)
EL (1,000 pcs/reel)
PRSP0020DC-A
RP
(FP-20DBV)
Note: Please consult the sales office for the above package availability.
Pin Arrangement
Clear1Q1D2D2Q3Q3D4D4QGNDQClearDCKDQQCKClearQClearCKDCKDClearQQClearCKDCKDClearQ24131211VCC8Q8D7D7Q6Q6D5D5QClockClearDCKDCKClearQ(Top view)
Rev.3.00, Jul.15.2005, page 1 of 6
元器件交易网74LS273
Function Table
Inputs Output
Clear Clock D Q
L X X L
H ↑ H H
H ↑ L L
H L X Q0
Notes: H; high level, L; low level, X; irrelevant
↑; transition from low to high level
Q0; level of Q before the indicated steady-state input conditions were established.
Block Diagram
1D2D3D4D5D6D7D8DClock (1)DQCKClearDQCKClearDQCKClearDQCKClearDQCKClearDQCKClearDQCKClearDQCKClearClear (2)1Q2Q3Q4Q5Q6Q7Q8Q
Absolute Maximum Ratings
Supply voltage
Input voltage
Power dissipation
Storage temperature
Item Symbol Ratings Unit
VCC 7 V
VIN 7 V
Tstg –65 to +150 °C
PT 400 mW
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Recommended Operating Conditions
Supply voltage
Output current
VCC 4.75 5.00 5.25 V
IOH — — –400 ?A
IOL — — 8 mA
?clock 0 — 30 MHz
tw (clock) 20 — —
tw (clear) 20 — —
ns
ns
Item Symbol Min Typ Max Unit
Operating temperature Topr –20 25 75 °C
Clock frequency
Clock pulse width
Clear pulse width
Data setup time
Clear (inactive-state) setup time
Data hold time
tsu (data) 20↑ — — ns
tsu (clear) 25↑ — — ns
th (data) 5↑ — — ns
Rev.3.00, Jul.15.2005, page 2 of 6
元器件交易网74LS273
Electrical Characteristics
(Ta = –20 to +75 °C)
Item Symbol min. typ.* max. Unit
VIH 2.0 — — V
Input voltage
VIL — — 0.8 V
Condition
Output voltage
Input current
Short-circuit output current
Supply current
Input clamp voltage
Notes: * VCC = 5 V, Ta = 25°C
** With all outputs open and 4.5 V applied to all data and clear inputs, ICC is measured after a momentary
ground, then 4.5 V is applied to clock.
VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V,
VOH 2.7 — — V
IOH = –400 ?A
— — 0.5 IOL = 8 mA
VCC = 4.75 V, VIH = 2 V,
VOL V
— — 0.4 IOL = 4 mA
VIL = 0.8 V
IIH — 20 ?A VCC = 5.25 V, VI = 2.7 V
IIL — –0.4 mA VCC = 5.25 V, VI = 0.4 V
0.1 mA VCC = 5.25 V, VI = 7 V II —
IOS –20 — –100 mA VCC = 5.25 V
ICC** — 17 27 mA VCC = 5.25 V
VIK — — –1.5 V VCC = 4.75 V, IIN = –18 mA
Switching Characteristics
(VCC = 5 V, Ta = 25°C)
Item Symbol Inputs min. typ. max. Unit Condition
Maximum clock frequency ?max Clock 30 40 — MHz
tPHL Clear — 18 27
CL = 15 pF, RL = 2 k?
ns
Propagation delay time
tPLH — 17 27
Clock
— 18 27 tPHL
Testing Method
Test Circuit
= 50?
= 50?DClockClearOutputQRLCL
Notes: 1. CL includes probe and jig capacitance.
2. All diodes are 1S2074(H).
Rev.3.00, Jul.15.2005, page 3 of 6
元器件交易网74LS273
Waveforms 1
tTLH90%1.3 V10%90%1.3 V10%tTHL3V1.3 VData0Vth3VtsutTLHClockthtTHL90%90%1.3 V1.3 V10%tsu10%1.3 V0VtwtPHLVOHtwtPLHQ1.3 V1.3 VVOL
Notes: Input pulse; tTLH ≤ 15 ns, tTHL ≤ 6 ns,
Clock input; PRR = 1 MHz, duty cycle 50%
Data input; PRR = 500 kHz, duty cycle 50%
Waveforms 2
tTHLClear90%1.3VtTLH90%1.3V10%twtTHLClocktPHLtwQ1.3VtPLH1.3VVOL90%1.3V10%tTLH90%1.3V10%3V0VVOH3V0V10%tw
Note: Input pulse: tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz.
Rev.3.00, Jul.15.2005, page 4 of 6
元器件交易网74LS273
Package Dimensions
JEITA Package CodeP-DIP20-6.3x24.5-2.54RENESAS CodePRDP0020AC-BPrevious CodeDP-20NEVMASS[Typ.]1.26gD201110.89b
310ZEReferenceSymbolDimension in MillimetersMinNom7.6224.506.3025.407.005.080.510.400.481.300.190°2.292.540.250.3115°2.791.272.540.56MaxAA
1eDEL1AA1bp3eb
pθe1cbcθeZ( Ni/Pd/Au plating )L
JEITA Package CodeP-SOP20-5.5x12.6-1.27RENESAS CodePRSP0020DD-BPrevious CodeFP-20DAVMASS[Typ.]0.31g*1D11FNOTE)1. DIMENSIONS\"*1 (Nom)\"AND\"*2\"DO NOT INCLUDE MOLD FLASH.2. DIMENSION\"*3\"DOES NOTINCLUDE TRIM OFFSET.20bpEHEIndex markReferenceSymbol*2cDimension in MillimetersMinNom12.605.50Max13.0Terminal cross section ( Ni/Pd/Au plating )1Ze*3DEA2A10.0010b
pxML10.100.202.20Abpb1cc10.340.400.460.150.200.25AθHE0°7.507.801.278°8.00θA
1yLexy0.120.150.800.501Detail FZLL0.701.150.90
Rev.3.00, Jul.15.2005, page 5 of 6
元器件交易网74LS273
JEITA Package CodeP-SOP20-7.5x12.8-1.27RENESAS CodePRSP0020DC-APrevious CodeFP-20DBVMASS[Typ.]0.52g*1D11FNOTE)1. DIMENSIONS\"*1 (Nom)\"AND\"*2\"@ DO NOT INCLUDE MOLD FLASH.2. DIMENSION\"*3\"DOES NOT@ INCLUDE TRIM OFFSET.20bp*2HEEIndex markReferenceSymbolcDimension in MillimetersMinNom12.807.50Max13.2Terminal cross section ( Ni/Pd/Au plating )1Ze*3DEA210b
pxML1A1Abpb1cc10.100.200.302.650.340.400.460.200.250.30AθHEe0°10.0010.401.278°10.65θA
1yLxyZ0.120.150.9350.401Detail FLL0.701.451.27
Rev.3.00, Jul.15.2005, page 6 of 6
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