FPGA可编程逻辑器件芯片5AGTFD3H3F35I4N中文规格书

2023年12月20日发(作者：奇瑞风云2报价)

StratixII ArchitectureFigure2– in Arithmetic Modecarry_indatae04-InputLUTadder0To general orlocal routingDQdataf0datacdatabdataaTo general orlocal routing4-InputLUTreg0dataddatae14-InputLUTadder1To general orlocal routingDQTo general orlocal routing4-InputLUTdataf1carry_outreg1While operating in arithmetic mode, the ALM can support simultaneous

use of the adder\'s carry output along with combinational logic outputs. In

this operation, the adder output is ignored. This usage of the adder with

the combinational logic output provides resource savings of up to 50% for

functions that can use this ability. An example of such functionality is a

conditional operation, such as the one shown in Figure2–12. The

equation for this example is:R = (X < Y) ? Y : XTo implement this function, the adder is used to subtract ‘Y’ from ‘X.’ If

‘X’ is less than ‘Y,’ the carry_out signal is ‘1.’ The carry_out signal is

fed to an adder where it drives out to the LAB local interconnect. It then

feeds to the LAB-wide syncload signal. When asserted, syncload

selects the syncdata input. In this case, the data ‘Y’ drives the

syncdata inputs to the registers. If ‘X’ is greater than or equal to ‘Y,’ the

syncload signal is de-asserted and ‘X’ drives the data port of the

x II Device Handbook, Volume 1

StratixII and StratixIIGX I/O BanksStratixII and

StratixIIGX I/O

BanksStratixII devices have eight general I/O banks and four enhanced

phase-locked loop (PLL) external clock output banks (Figure4–21). I/O

banks 1, 2, 5, and 6 are on the left or right sides of the device and I/O

banks 3, 4, and 7 through 12 are at the top or bottom of the 4–xII I/O Banks Notes(1), (2), (3), (4), (5), (6), (7)DQS8TVREF0B3DQS7TVREF1B3DQS6TVREF3B3DQS5TVREF4B3VREF2B3PLL11Bank 11PLL5Bank 9DQS4TVREF0B4DQS3TVREF1B4DQS2TVREF2B4DQS1TVREF3B4DQS0TVREF4B4PLL7Bank 3VREF4B2PLL10Bank 4VREF0B5Bank

2Bank

5PLL4PLL3VREF2B2VREF1B2VREF0B2PLL1PLL2VREF4B1I/O banks 1, 2, 5 & 6 support LVTTL, LVCMOS,

2.5-V, 1.8-V, 1.5-V, SSTL-2, SSTL-18 Class I,

HSTL-18 Class I, HSTL-15 Class I, LVDS, and

HyperTransport standards for input and output

operations. HSTL-18 Class II, HSTL-15-Class II,

SSTL-18 Class II standards are only supported

for input 3B1Bank

1Bank

6PLL9VREF2B1This I/O bank supports LVDS

and LVPECL standards for inputclock operations. DifferentialHSTL and differential SSTL

standards are supported for both

input and output I/O bank supports LVDS

and LVPECL standards for inputclock operations. DifferentialHSTL and differential SSTL

standards are supported for both

input and output 1B1VREF0B1Bank 8PLL8VREF4B8DQS8BVREF3B8VREF2B8VREF1B8VREF0B8DQS5BDQS7BDQS6BBank 12Bank 10Bank 7VREF4B7DQS4BVREF3B7DQS3BVREF2B7DQS2BVREF1B7DQS1BVREF0B7DQS0BPLL12PLL6Notes to Figure4–21:(1)(2)(3)Figure4–21

is a top view of the silicon die that corresponds to a reverse view for flip-chip packages. It is a graphical

representation only. Refer to the pin list and QuartusII software for exact ing on the size of the device, different device members have different numbers of VREF 9 through 12 are enhanced PLL external clock output banks. These PLL banks utilize the adjacent VREF group

when voltage-referenced standards are implemented. For example, if an SSTL input is implemented in PLL bank

10, the voltage level at VREFB7 is the reference voltage level for the SSTL ential HSTL and differential SSTL standards are available for bidirectional operations on DQS pin and

input-only operations on PLL clock input pins; LVDS, LVPECL, and HyperTransport standards are available forinput-only operations on PLL clock input pins. Refer to the “Differential I/O Standards” on page4–10 for more

sII software does not support differential SSTL and differential HSTL standards at left/right I/O banks.

Refer to the “Differential I/O Standards” on page4–10 if you need to implement these standards at these I/O 11 and 12 are available only in EP2S60, EP2S90, EP2S130, and EP2S180 7, 8, 9 10, 11, and 12 are available only in EP2S60, EP2S90, EP2S130, and EP2S180 devices.(4)(5)(6)(7)Stratix II Device Handbook, Volume 2VREF4B6VREF3B6VREF2B6I/O banks 7, 8, 10 & 12 support allsingle-ended I/O standards anddifferential I/O standards except for

HyperTransport technology for

both input and output 1B6VREF0B6VREF4B5VREF3B5VREF2B5This I/O bank supports LVDS

and LVPECL standards for inputclock operations. DifferentialHSTL and differential SSTL

standards are supported for both

input and output operations.I/O banks 3, 4, 9 & 11 support allsingle-ended I/O standards anddifferential I/O standards except for

HyperTransport technology for

both input and output I/O bank supports LVDS

and LVPECL standards for inputclock operations. DifferentialHSTL and differential SSTL

standards are supported for both

input and output 3B2VREF1B5

Adaptive Logic Modulesarithmetic chain runs vertically allowing fast horizontal connections to

TriMatrix memory and DSP blocks. A shared arithmetic chain can