ST USBLC6-4SC6 数据手册

2024年2月27日发(作者：二十万左右最好的轿车)

查询USBLC6-4SC6供应商?USBLC6-4SC6VERY LOW CAPACITANCEESD PROTECTIONASD(Application Specific Devices)MAIN APPLICATIONS■USB2.0 ports up to 480Mb/s (high speed)■Backwards compatible with USB1.1 low and

full speed■Ethernet port: 10/100Mb/s■SIM card protection■Video line protection■Portable electronicsDESCRIPTIONThe USBLC6-4SC6 is a monolithic ApplicationSpecific Discrete dedicated to ESD protection ofhigh speed interfaces, such as USB2.0, Ethernetlinks and Video lines.

Its very low line capacitance secures a high levelof signal integrity without compromising inprotecting sensitive chips against the moststringent characterized ESD ES■4 data lines protection■Protects VBUS■Very low capacitance: 3pF typ.■SOT23-6L package■RoHS compliantBENEFITS■Very low capacitance between lines to GND foroptimized data integrity and speed■Low PCB space consuming, 9mm? maximumfoot print■Enhanced ESD protection■IEC61000-4-2 level 4 compliance guaranteedat device level, hence greater immunity atsystem level■ESD protection of VBUS. Allows ESD currentflowing to Ground when ESD event occurs ondata line■High reliability offered by monolithic integration■Low leakage current for longer operation ofbattery powered devices■Fast response time■Consistent D+ / D- signal balance:- Best capacitance matching tolerance I/O to GND = 0.015pF- Compliant with USB 2.0 requirements < 1pFSOT23-6LFigure 1: Functional DiagramI/O116I/O4GND25VBUSI/O234I/O3Table 1: Order CodePart NumberUSBLC6-4SC6MarkingUL46COMPLIES WITH THE FOLLOWING STANDARDS:■IEC61000-4-2 level4:15kV(air discharge)8kV(contact discharge)February 2005REV. 21/10

USBLC6-4SC6Table 2: Absolute RatingsSymbolVPPTstgTjTLPeak pulse voltageStorage temperature rangeMaximum junction temperatureLead solder temperature (10 seconds duration)ParameterAt device level:IEC61000-4-2 air dischargeIEC61000-4-2 contact dischargeMIL STD883C-Method 3015-6Value151525-55 to +150125260UnitkV°C°C°CTable 3: Electrical Characteristics (Tamb = 25°C)SymbolVRMIRMVBRVFParameterReverse stand-off voltageLeakage currentVRM = 5V60.86121730.015Capacitance between I/OVR = 1.65V1.850.042.74Test .52UnitV?AVVVVpFBreakdown voltage between VBUS

IR = 1mAand GNDForward voltageIR = 10mAIPP = 1A, tp = 8/20?sAny I/O pin to GNDIPP = 5A, tp = 8/20?sAny I/O pin to GNDVCLClamping voltageCi/o-GND?Ci/o-GNDCi/o-i/o?Ci/o-i/oCapacitance between I/O and GNDVR = 1.65VpF2/10

USBLC6-4SC6Figure 2: Capacitance versus voltage (typicalvalues)C(pF)5.04.54.03.5C=I/O-GNDF=1MHzV=30mVT=25°CFigure 3: Line capacitance versus frequency(typical values)C(pF)5.04.5V=0VV=30mVT=25°C4.03.5V=1.65V3.02.5C=I/O-I/O3.02.52.01.51.02.01.51.00.50.00.00.51.01.52.02.53.03.54.04.55.0Data line voltage (V)0.50.0110F(MHz)1001000Figure 4: Relative variation of leakage currentversus junction temperature (typical values)IRM[Tj] /IRM[Tj=25°C]100V=5VFigure 5: Frequency responseUSBLC6-4SC6(50?)1012550Tj(°C)75100125F(Hz)3/10

USBLC6-4SC6TECHNICAL INFORMATION1. SURGE PROTECTIONThe USBLC6-4SC6 is particularly optimized to perform surge protection based on the rail to rail clamping voltage VCL can be calculated as follow :VCL+ = VBUS + VF for positive surgesVCL- = - VF for negative surgeswith: VF = VT + (VF forward drop voltage) / (VT forward drop threshold voltage)We assume that the value of the dynamic resistance of the clamping diode is typically:Rd = 1.4? and VT = 1.2V.

For an IEC61000-4-2 surge Level 4 (Contact Discharge: Vg=8kV, Rg=330?), VBUS = +5V, and if in firstapproximation, we assume that : Ip = Vg / Rg = , we find:VCL+ = +39VVCL- = -34VNote: the calculations do not take into account phenomena due to parasitic inductances.2. SURGE PROTECTION APPLICATION EXAMPLEIf we consider that the connections from the pin VBUS to VCC and from GND to PCB GND are done bytwo tracks of 10mm long and 0.5mm large; we assume that the parasitic inductances Lw of these tracksare about 6nH. So when an IEC61000-4-2 surge occurs, due to the rise time of this spike (tr=1ns), thevoltage VCL has an extra value equal to / dI/dt is calculated as: dI/dt = Ip/tr = 24 A/nsThe overvoltage due to the parasitic inductances is: /dt = 6 x 24 = 144VBy taking into account the effect of these parasitic inductances due to unsuitable layout, the clampingvoltage will be :VCL+ = +39 + 144 = 183VVCL- = -34 - 144 = -178VWe can reduce as much as possible these phenomena with simple layout ’s the reason why some recommendations have to be followed (see paragraph “How to ensure a goodESD protection”).Figure 6: ESD behavior; parasitic phenomena due to unsuitable layoutVCL+ESDSURGEVBUSLw+VCCVFI/Otr=1ns183VLwdidtLwdidtPOSITIVESURGEVCC+VFtVI/OLwdidtdiVCL +=VBUS+VF+Lwdtsurge >0disurge <0VCL -=-VF-Lwdttr=1ns-VF-LwdidtNEGATIVESURGEtGND-178VVCL-4/10

USBLC6-4SC63. HOW TO ENSURE A GOOD ESD PROTECTIONWhile the USBLC6-4SC6 provides a high immunity to ESD surge, an efficient protection depends on thelayout of the board. In the same way, with the rail to rail topology, the track from the VBUS pin to the powersupply +VCC and from the VBUS pin to GND must be as short as possible to avoid overvoltages due toparasitic phenomena (see figure 6).It’s often harder to connect the power supply near to the USBLC6-4SC6 unlike the ground thanks to theground plane that allows a short ensure the same efficiency for positive surges when the connections can’t be short enough, werecommend to put close to the USBLC6-4SC6, between VBUS and ground, a capacitance of 100nF toprevent from these kinds of overvoltage disturbances (see figure 7).The add of this capacitance will allow a better protection by providing during surge a constant figures 8, 9 and 10 show the improvement of the ESD protection according to the recommendations

described 7: ESD behavior: optimized layout andadd of a capacitance of 100nFFigure 8: ESD behavior: measurementsconditions (with coupling capacitance)ESDSURGEVCL+ESDSURGELwC=100nFTEST BOARDUSBLC6-4SC6REF2=+VCCPOSITIVESURGEI/OVCL+=VCC+VFsurge >0VI/O+5VVCL- =-VFsurge <0NEGATIVESURGEREF1=GNDVCL-C=100nFFigure 9: Remaining voltage after theUSBLC6-4SC6 during positive ESD surgeFigure 10: Remaining voltage after theUSBLC6-4SC6 during negative ESD surgeIMPORTANT:A main precaution to take is to put the protection device closer to the disturbance source (generally theconnector).Note: The measurements have been done with the USBLC6-4SC6 in open circuit.5/10

USBLC6-4SC64. CROSSTALK BEHAVIOR4.1. Crosstalk phenomenaFigure 11: Crosstalk phenomenaRG1Line 1α1VG1+β12VG2VG1RG2Line 2RL1VG2RL2α2VG2+β21VG1DRIVERSRECEIVERSThe crosstalk phenomena are due to the coupling between 2 lines. The coupling factor (β12 or β21)increases when the gap across lines decreases, particularly in silicon dice. In the example above theexpected signal on load RL2 is α2VG2, in fact the real voltage at this point has got an extra value β part of the VG1 signal represents the effect of the crosstalk phenomenon of the line 1 on the line phenomenon has to be taken into account when the drivers impose fast digital data or high frequencyanalog signals in the disturbing line. The perturbed line will be more affected if it works with low voltagesignal or high load impedance (few k?).Figure 12: Analog crosstalk measurementsTRACKING GENERATORTEST BOARDSPECTRUM ANALYSER50?+5VVgVinC=100nFVout50?Figure 12 gives the measurement circuit for the analog application. In usual frequency range of analogsignals (up to 240MHz) the effect on disturbed line is less than -55 dB (please see figure 13).Figure 13: Analog crosstalk resultsAs the USBLC6-4SC6 is designed to protect high

speed data lines, it must ensure a good transmis-sion of operating signals. The frequency response

(figure 5) gives attenuation information and shows

that the USBLC6-4SC6 is well suitable for data

line transmission up to 480 Mbit/s while it works

as a filter for undesirable signals like GSM

(900MHz) frequencies, for instance.6/10

USBLC6-4SC65. APPLICATION EXAMPLESFigure 14: USB2.0 port application diagram using USBLC6-4SC6+ 3.3VDEVICE-UPSTREAMRPUTRANSCEIVERSW2VBUSRX LS/FS+RX HS+TX HS+RX LS/FS -RX HS -TX HS -GNDTX LS/FS+TX LS/FS -+ 5VUSBconnectorProtectingBus SwitchHUB-DOWNSTREAMTRANSCEIVERSW1VBUSD+D-RSRSRPDUSBLC6-2SC6VBUSRX LS/FS+RX HS+TX HS+RX LS/FS -RX HS -TX HS -GNDRSRSRPDGNDTX LS/FS+TX LS/FS -+ 3.3VDEVICE-UPSTREAMRPUTRANSCEIVERSW2VBUSRX LS/FS+RX HS+TX HS+RX LS/FS -RX HS -TX HS -GNDTX LS/FS+TX LS/FS -SW1USBconnectorVBUSD+D-RSRSUSBLC6-2P6RX LS/FS+RX HS+TX HS+RX LS/FS -RX HS -TX HS -GNDRSGNDTX LS/FS+TX LS/FS -USBLC6-4SC6RPDRSRPDModeLow Speed LSFull Speed FSHigh Speed HSSW1OpenClosedSW2ClosedOpenClosed then openOpenFigure 15: T1/E1/Ethernet protectionTxSMP75-8USBLC6-4SC6+VCC100nFDATATRANSCEIVERRxSMP75-87/10

USBLC6-4SC66. PSPICE MODELFigure 16 shows the PSPICE model of one USBLC6-4SC6 cell. In this model, the diodes are defined bythe PSPICE parameters given in figure 16: PSPICE modelLbondsot23100mLpinsot23LvccRvccVccMODEL = Dhighio1io2io3io4Lpinsot23Lpinsot23Lpinsot23Lpinsot23Lbondsot23100mLbondsot23100mLbondsot23100mLbondsot23100mMODEL = DhighMODEL = DhighMODEL = DhighMODEL = DzenerMODEL = DlowMODEL = DlowMODEL = DlowMODEL = DlowLbondsot23100mLpinsot23LgndRgndLbondsot23100mNote: This simulation model is available only for an ambient temperature of 27° 17: PSPICE parametersFigure 18: USBLC6-4SC6 PCB layoutconsiderationsDlowBVCJ0IBVIKFISISRNMRSVJTT502.4p1m0.03855.2p100p1.620.33330.380.60.1uDhigh502.4p1m0.0182.27f100p1.130.33330.630.60.1uDzener7.320p1m2.423.21p100p1.240.33330.420.60.1uLbondsot23Lpinsot23RgndLgndRvccLvcc0.564n0.15nD+1350m100p350m100p1D-1GNDD+2D-2VBUSCBUS= 100nFUSBLC6-4SC68/10

USBLC6-4SC6Figure 19: SOT23-6L Package Mechanical metersMin.0.9000.900.350.092.801.500.952.600.100°3.000.1020.600.00410°0°.0.10Min.01.450.0351.300.0350.500.0140.200.0043.050.1101.750.0590.0370.1180.02410°.0.0570.0040.0510.020.0080.1200.069eBeDA1A2bCA2DEecA1θHLθLHFigure 20: Foot Print Dimensions (in millimeters)0.601.203.502.300.951.10Table 4: Ordering InformationOrdering codeUSBLC6-4SC6MarkingUL46PackageSOT23-6LWeight16.7 mgBase qty3000Delivery modeTape & reelTable 5: Revision HistoryDate10-Dec-200428-Feb-2005Revision12First layout update. No content ption of Changes9/10

USBLC6-4SC6Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequencesof use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is grantedby implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subjectto change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are notauthorized for use as critical components in life support devices or systems without express written approval of ST logo is a registered trademark of STMicroelectronics.

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