ST AN4057 Application note 数据手册

2024年2月27日发(作者：大众途观口碑评价)

AN4057Application noteSPC560Pxx, SPC56APxx power up HW guidelineINTRODUCTIONThis application note is addressed to system hardware designers using

STMicroelectronics? SPC560Pxx/SPC56APxx microcontrollers It gives design references to

ensure a reliable microcontroller power up sequence also in the condition of an offset

voltage on the high voltage regulator supply pin VDD_HV_REG at power use of the SPC560Pxx/SPC56APxx internal voltage regulator requires a specific design

ST approved ballasts with the recommended supporting network described in the latest

revision of the device data sheet (for further details see SectionAppendix A: Additional

information). It is important to respect the power on sequence conditions, ensuring a

monotonic supply ramp starting at ground level and respecting the min and max slew rate

on VDD_HV_ application note covers:■■■Recommended power on sequence conditionsPossible deviations injecting an offset voltage on VDD_HV_REG and its impact on

microcontroller power upOptional proposals to eliminate the effect of offset voltage on VDD_HV_REG pinMarch 2012Doc ID 022842 Rev 11/

Contents AN4057Contents1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.1Power up sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Offset voltage on VDD_HV_REG and voltage regulator circuitry . . . . . . . 62.1Offset voltage on VDD_HV_REG: problem description . . . . . . . . . . . . . . . . . 62.1.12.1.2Possible application paths to induce a VDD_HV_REG offset voltage . . . . . 6Battery short to pin on connector of microcontroller board . . . . . . . . . . . 62.2HW guidelines for high/low voltage supply of the internal regulator with offset

voltage on VDD_HV_REG 72.2.12.2.2Resistors partition network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7VDD_HV_REG pin active path to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . 83SPC560Pxx/SPC56APxx devices affected . . . . . . . . . . . . . . . . . . . . . . 10Appendix AAdditional information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11A.1Reference document. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122/13Doc ID 022842 Rev 1

AN4057List of tablesList of tablesTable or partition network values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8SPC560Pxx/SPC56APxx device affected from VDD_HV_REG

offset issue . . . . . . . . . . . . . 10Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Doc ID 022842 Rev 13/13

List of figures AN4057List of figuresFigure voltage on VDD_HV_REG from SPC560Pxx/SPC56APxx input pin . . . . . . . . . . . . . . . 6Battery short to pin on connector of microcontroller board. . . . . . . . . . . . . . . . . . . . . . . . . . 7Resistors partition network. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Active path to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94/13Doc ID 022842 Rev 1

AN4057Overview1 OverviewThese SPC560Pxx /SPC56APxx microcontrollers are members of a new microcontroller

family built on the Power Architecture?. The device is supplied externally with a single

voltage supply, which can be either 5V or 3.3V depending on application requirements.

Internally the chip operates with 2 supply voltages, namely the main supply (5V or 3.3V)

and the core logic supply (1.2V).This document provides guideline for the recommended configuration of the high and low

voltage supply for the internal regulator in order to ensure the correct power up sequence of

the note describes application fault conditions that may offset VDD_HV_REG significantly and

mitigating circuitries to ensure reliable power up in case of these fault conditions. The

standard supply circuitry and sequence that use in the recommended conditions of initial

power up on VDD_HV_REG pin starting from ground level are described in the

SPC560Pxx/SPC56APxx data sheet (for further details see SectionAppendix A: Additional

information).

Possible causes of fault conditions injecting an offset voltage on VDD_HV_REG pin are

described in the following list:●●Supply microcontrollers I/O VIN while the microcontroller is switched off with shorted

supply for VDD_HV_REG

and VDD_HV_IO pinsOffset voltage injected on VDD_HV_REG

by external signal(s) shorted to battery.1.1 Power up sequencingPreventing an overstress event or a malfunction within and outside the device, the

SPC560Pxx/SPC56APxx implements a specific power up sequence, as described in the

data sheet, to ensure each module is started only when all conditions for switching it ON are

available.

In case of a fault condition on the application board, that sequence may not be respected,

causing the device not to exit the power up.

Two possible fault conditions are described in the following sections. However, if the fault

cause is removed, the device (while within the absolute maximum ratings) works again,

without getting damaged, powering up ID 022842 Rev 15/13

Offset voltage on VDD_HV_REG and voltage regulator circuitry AN40572

2.1

Offset voltage on VDD_HV_REG and voltage regulator

circuitryOffset voltage on VDD_HV_REG: problem descriptionVDD_HV_REG offset on the devices SPC560Pxx/SPC56APxx, before the module is powered

up, may in some cases prevent the power up device correctly.A VDD_HV_REG

offset before a correct power up supply sequence can set the POR device

logic to an undefined state, preventing the internal logic to switch correctly and initialize the

internal VDD_LV circuitry. The internal regulator remains in power down. The consequence is

that the microcontroller is not able to exit reset.2.1.1 Possible application paths to induce a VDD_HV_REG offset voltageFigure1 describes a GPIO configuration with the pin connected to an externally supplied

signal (Vbatt).If Vbatt

is powered while MCU VDD is not yet provided, GPIO protection circuitry (diode)

induces a voltage on VDD_HV_ the case VDD_HV_IO is directly connected to VDD_HV_REG, the induced voltage is

propagated to the internal regulator. The same consideration is done when using an

external diode, D1 in Figure1, connecting GPIO VIN to voltage on VDD_HV_REG from SPC560Pxx/SPC56APxx input pin9\'\'