2023年12月31日发(作者：别克凯越2009款)
Ultralow Offset VoltageOperational AmplifierOP07PIN CONFIGURATION
VOS TRIM–IN+INV–1234FEATURES
Low VOS: 75 μV maximum
Low VOS drift: 1.3 μV/°C maximum
Ultrastable vs. time: 1.5 μV per month maximum
Low noise: 0.6 μV p-p maximum
Wide input voltage range: ±14 V typical
Wide supply voltage range: 3 V to 18 V
125°C temperature-tested dice
OP078765VOS TRIMV+OUT00316-001NCNC = NO CONNECT
Figure 1.
APPLICATIONS
Wireless base station control circuits
Optical network control circuits
Instrumentation
Sensors and controls
Thermocouples
Resistor thermal detectors (RTDs)
Strain bridges
Shunt current measurements
Precision filters
GENERAL DESCRIPTION
The OP07 has very low input offset voltage (75 μV maximum for
OP07E) that is obtained by trimming at the wafer stage. These
low offset voltages generally eliminate any need for external
nulling. The OP07 also features low input bias current (±4 nA for
the OP07E) and high open-loop gain (200 V/mV for the OP07E).
The low offset and high open-loop gain make the OP07
particularly useful for high gain instrumentation applications.
V+7R2A1R1A1(OPTIONALNULL)8R2B1The wide input voltage range of ±13 V minimum combined
with a high CMRR of 106 dB (OP07E) and high input
impedance provide high accuracy in the noninverting circuit
configuration. Excellent linearity and gain accuracy can be
maintained even at high closed-loop gains. Stability of offsets
and gain with time or variations in temperature is excellent. The
accuracy and stability of the OP07, even at high gain, combined
with the freedom from external nulling have made the OP07 an
industry standard for instrumentation applications.
The OP07 is available in two standard performance grades. The
OP07E is specified for operation over the 0°C to 70°C range,
and the OP07C is specified over the ?40°C to +85°C
temperature range.
The OP07 is available in epoxy 8-lead PDIP and 8-lead narrow
SOIC packages. For CERDIP and TO-99 packages and standard
microcircuit drawing (SMD) versions, see the OP77.
C1R1BR7Q19Q9Q10Q11Q12C2Q17R10Q20Q15Q14Q13R6Q18R800316-002R9OUT6Q16Q7NONINVERTINGINPUT3INVERTINGINPUTR3Q5Q3Q1Q21R424V–Q22Q23Q24Q6Q8Q4Q27Q26Q2Q25C3R51R2A AND R2B ARE ELECTRONICALLY ADJUSTED ON CHIP AT FACTORY FOR MINIMUM INPUT OFFSET VOLTAGE.
Figure 2. Simplified Schematic
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, : 781.329.4700
Fax: 781.461.3113 ?2006-2009 Analog Devices, Inc. All rights reserved.
OP07
Absolute Maximum Ratings ............................................................6 Thermal Resistance .......................................................................6 6 Typical Performance Characteristics ..............................................7 Typical Applications ....................................................................... 11 Applications Information .......................................................... 12 Outline Dimensions ....................................................................... 13 Ordering Guide .......................................................................... 14 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Pin Configuration ............................................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 OP07E Electrical Characteristics ............................................... 3 OP07C Electrical Characteristics ............................................... 4 REVISION HISTORY
7/09—Rev. D. to Rev E
Changes to Figure 29 Caption ....................................................... 11
Changes to Ordering Guide .......................................................... 14
7/06—Rev. C. to Rev D
Changes to Features .......................................................................... 1
Changes to General Description .................................................... 1
Changes to Specifications Section .................................................. 3
Changes to Table 4 ............................................................................ 6
Changes to Figure 6 and Figure 8 ................................................... 7
Changes to Figure 13 and Figure 14 ............................................... 8
Changes to Figure 20 ........................................................................ 9
Changes to Figure 21 to Figure 25 ................................................ 10
Changes to Figure 26 and Figure 30 ............................................. 11
Replaced Figure 28 ......................................................................... 11
Changes to Applications Information Section ............................ 12
Updated Outline Dimensions ....................................................... 13
Changes to Ordering Guide .......................................................... 14
8/03—Rev. B to Rev. C
Changes to OP07E Electrical Specifications .................................. 2
Changes to OP07C Electrical Specifications ................................. 3
Edits to Ordering Guide ................................................................... 5
Edits to Figure 6 ................................................................................. 9
Updated Outline Dimensions ....................................................... 11
3/03—Rev. A to Rev. B
Updated Package Titles ...................................................... Universal
Updated Outline Dimensions ....................................................... 11
2/02—Rev. 0 to Rev. A
Edits to Features ................................................................................. 1
Edits to Ordering Guide ................................................................... 1
Edits to Pin Connection Drawings ................................................. 1
Edits to Absolute Maximum Ratings .............................................. 2
Deleted Electrical Characteristics .............................................. 2–3
Deleted OP07D Column from Electrical Characteristics ....... 4–5
Edits to TPCs ................................................................................ 7–9
Edits to High-Speed, Low VOS Composite Amplifier ................... 9
Rev. E | Page 2 of 16
OP07SPECIFICATIONS
OP07E ELECTRICAL CHARACTERISTICS
VS = ±15 V, unless otherwise noted.
Table 1.
Parameter
IPUT CHARACTERISTICS
TA = 25°C
Input Offset Voltage1Long-Term VOS Stability2Input Offset Current
Input Bias Current
Input Noise Voltage
Input Noise Voltage Density
Input Noise Current
Input Noise Current Density
Input Resistance, Differential Mode4Input Resistance, Common Mode
Input Voltage Range
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Large Signal Voltage Gain
N0°C ≤ TA ≤ 70°C
Input Offset Voltage1Voltage Drift Without External Trim4Voltage Drift with External Trim3Input Offset Current
Input Offset Current Drift
Input Bias Current
Input Bias Current Drift
Input Voltage Range
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Large Signal Voltage Gain
OUTPUT CHARACTERISTICS
TA = 25°C
Output Voltage Swing
0°C ≤ TA ≤ 70°C
Output Voltage Swing
Symbol
VOS
VOS/Time
IOS
IB
en p-p
en
In p-p
In
RIN
RINCM
IVR
CMRR
PSRR
AVO
VOS
TCVOS
TCVOSN
IOS
TCIOS
IB
TCIB
IVR
CMRR
PSRR
AVO
VO
VO
Conditions
0.1 Hz to 10 Hz3fO = 10 Hz
fO = 100 Hz3fO = 1 kHz
fO = 10 Hz
fO = 100 Hz3fO = 1 kHz
VCM = ±13 V
VS = ±3 V to ±18 V
RL ≥ 2 kΩ, VO = ±10 V
RL ≥ 500 Ω, VO = ±0.5 V, VS = ±3 V4
RP = 20 kΩ
VCM = ±13 V
VS = ±3 V to ±18 V
RL ≥ 2 kΩ, VO = ±10 V
RL ≥ 10 kΩ
RL ≥ 2 kΩ
RL ≥ 1 kΩ
RL ≥ 2 kΩ
Min Typ Max Unit
30 75 μV
0.3 1.5 μV/Month
0.5 3.8 nA
±1.2 ±4.0 nA
0.35 0.6 μV p-p
10.3 18.0 nV/√Hz
10.0 13.0 nV/√Hz
9.6 11.0 nV/√Hz
14 30 pA p-p
0.32 0.80 pA/√Hz
0.14 0.23 pA/√Hz
0.12 0.17 pA/√Hz
15 50 MΩ
160 GΩ
±13 ±14 V
106 123 dB
5 20 μV/V
200 500 V/mV
150 400 V/mV
45 130 μV
0.3 1.3 μV/°C
0.3 1.3 μV/°C
0.9 5.3 nA
8 35 pA/°C
±1.5 ±5.5 nA
13 35 pA/°C
±13 ±13.5 V
103 123 dB
7 32 μV/V
180 450 V/mV
±12.5 ±13.0 V
±12.0 ±12.8 V
±10.5 ±12.0 V
±12 ±12.6 V
Rev. E | Page 3 of 16
OP07
Symbol
SR
BW
RO
Pd
Conditions
RL ≥ 2 kΩ3AVOL = 15VO = 0, IO = 0
VS = ±15 V, No load
VS = ±3 V, No load
RP = 20 kΩ
Parameter
DYAMIC PERFORMACE
TA = 25°C
Slew Rate
Closed-Loop Bandwidth
Open-Loop Output Resistance
Power Consumption
Offset Adjustment Range
12Min Typ Max Unit
0.1 0.3 V/μs
0.4 0.6 MHz
60 Ω
75 120 mW
4 6 mW
±4 mV
Input offset voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power.
Long-term input offset voltage stability refers to the averaged trend time of VOS vs. the time over extended periods after the first 30 days of operation. Excluding the
initial hour of operation, changes in VOS during the first 30 operating days are typically 2.5 μV. Refer to the Typical Performance Characteristics section. Parameter is
sample tested.
3 Sample tested.
4 Guaranteed by design.
5 Guaranteed but not tested.
OP07C ELECTRICAL CHARACTERISTICS
VS = ±15 V, unless otherwise noted.
Table 2.
Parameter
INPUT CHARACTERISTICS
TA = 25°C
Input Offset Voltage1
Long-Term VOS Stability2
Input Offset Current
Input Bias Current
Input Noise Voltage
Input Noise Voltage Density
NInput Noise Current
NInput Noise Current Density
Input Resistance, Differential Mode4
Input Resistance, Common Mode
Input Voltage Range
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Large Signal Voltage Gain
?40°C ≤ TA ≤ +85°C
Input Offset Voltage1Voltage Drift Without External Trim4Voltage Drift with External Trim3Input Offset Current
Input Offset Current Drift
Input Bias Current
Input Bias Current Drift
Input Voltage Range
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Large Signal Voltage Gain
Symbol Conditions
VOS
VOS/Time
IOS
IB
en p-p 0.1 Hz to 10 Hz3
en fO = 10 Hz
fO = 100 Hz3
fO = 1 kHz
In p-p
In fO = 10 Hz
fO = 100 Hz3
fO = 1 kHz
RIN
RINCM
IVR
CMRR VCM = ±13 V
PSRR VS = ±3 V to ±18 V
AVO RL ≥ 2 kΩ, VO = ±10 V
RL ≥ 500 Ω, VO = ±0.5 V, VS = ±3 V4
VOS
TCVOS
TCVOSN RP = 20 kΩ
IOS
TCIOS
IB
TCIB
IVR
CMRR VCM = ±13 V
PSRR VS = ±3 V to ±18 V
AVO RL ≥ 2 kΩ, VO = ±10 V
Rev. E | Page 4 of 16
Min Typ Max Unit
60 150 μV
0.4 2.0 μV/Month
0.8 6.0 nA
±1.8 ±7.0 nA
0.38 0.65 μV p-p
10.5 20.0 nV/√Hz
10.2 13.5 nV/√Hz
9.8 11.5 nV/√Hz
15 35 pA p-p
0.35 0.90 pA/√Hz
0.15 0.27 pA/√Hz
0.13 0.18 pA/√Hz
8 33 MΩ
120 GΩ
±13 ±14 V
100 120 dB
7 32 μV/V
120 400 V/mV
100 400 V/mV
85 250 μV
0.5 1.8 μV/°C
0.4 1.6 μV/°C
1.6 8.0 nA
12 50 pA/°C
±2.2 ±9.0 nA
18 50 pA/°C
±13 ±13.5 V
97 120 dB
10 51 μV/V
100 400 V/mV
OP07Symbol
VO
VO
SR
BW
RO
Pd
Conditions
RL ≥ 10 kΩ
RL ≥ 2 kΩ
RL ≥ 1 kΩ
RL ≥ 2 kΩ
RL ≥ 2 kΩ3
AVOL = 15
VO = 0, IO = 0
VS = ±15 V, No load
VS = ±3 V, No load
RP = 20 kΩ
Min
±12.0
±11.5
±12
0.1
0.4
Typ
±13.0
±12.8
±12.0
±12.6
0.3
0.6
60
80
4
±4
Max
150
8
Unit
V
V
V
V
V/μs
MHz
Ω
mW
mW
mV
Parameter
OUTPUT CHARACTERISTICS
TA = 25°C
Output Voltage Swing
?40°C ≤ TA ≤ +85°C
Output Voltage Swing
DYNAMIC PERFORMANCE
TA = 25°C
Slew Rate
Closed-Loop Bandwidth
Open-Loop Output Resistance
Power Consumption
Offset Adjustment Range
12 Input offset voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power.
Long-term input offset voltage stability refers to the averaged trend time of VOS vs. the time over extended periods after the first 30 days of operation. Excluding the
initial hour of operation, changes in VOS during the first 30 operating days are typically 2.5 μV. Refer to the Typical Performance Characteristics section. Parameter is
sample tested.
3 Sample tested.
4 Guaranteed by design.
5 Guaranteed but not tested.
Rev. E | Page 5 of 16
OP07
Stresses above those listed under Absolute Maximum Ratings
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Ratings
may cause permanent damage to the device. This is a stress
Supply Voltage (VS)
±22 V
rating only; functional operation of the device at these or any
1Input Voltage
±22 V
other conditions above those indicated in the operational
Differential Input Voltage
±30 V
section of this specification is not implied. Exposure to absolute
Output Short-Circuit Duration Indefinite
maximum rating conditions for extended periods may affect
Storage Temperature Range
device reliability.
S and P Packages
?65°C to +125°C
THERMAL RESISTANCE
Operating Temperature Range
θJA is specified for the worst-case conditions, that is, a device
OP07E
0°C to 70°C
soldered in a circuit board for surface-mount packages.
OP07C
?40°C to +85°C
Junction Temperature
150°C
Table 4. Thermal Resistance
Lead Temperature, Soldering (60 sec)
300°C
Package Type θJA θJC Unit
1
For supply voltages less than ±22 V, the absolute maximum input voltage is
equal to the supply voltage.
8-Lead PDIP (P-Suffix)
8-Lead SOIC_N (S-Suffix)
103
158
43
43
°C/W
°C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. E | Page 6 of 16
OPOPEN-LOOP
GAIN
(V/mV)76-003TYPICAL PERFORMANCE CHARACTERISTICS
1.0MAXIMUM
ERROR
REFERRED
TO
INPUT
(mV)VS = ±15VVS = ±15VTA = 25°C0.80.60.4OP07C0.2OP07E1k10k100k0-00800316-0070–75–50–2550100TEMPERATURE (°C)MATCHED OR UNMATCHED SOURCE RESISTANCE (?)Figure 3. Open-Loop Gain vs. Temperature
301.2Figure 6. Maximum Error vs. Source Resistance
MAXIMUM
ERROR
REFERRED
TO
INPUT
(mV)VS = ±15V0°C ≤ TA ≤ 70°C1.0VS = ±15VTA = 25°C, TA = 70°C25ABSOLUTE
CHANGE
IN
INPUTOFFSET
VOLTAGE
(?V)200.81510THERMALSHOCKRESPONSEBAND0.60.4OP07C0.2OP07E01001k10k100k5DEVICE IMMERSEDIN 70°C OIL BATH02040TIME (Seconds)6-0040–20MATCHED OR UNMATCHED SOURCE RESISTANCE (?)Figure 4. Offset Voltage Change due to Thermal Shock
2530VS = ±15VTA = 25°CABSOLUTE
CHANGE
IN
INPUTOFFSET
VOLTAGE
(?V)Figure 7. Maximum Error vs. Source Resistance
AT |VDIFF| ≤ 1.0V, | IB| ≤ 7nA (OP07C)VS = ±15VTA = 25°CNONINVERTING
INPUT
BIAS
CURRENT
(nA)450015010OP07COP07E–105–2000123–30–30–20–100102030TIME AFTER SUPPLY TURN-ON (Minutes)DIFFERENTIAL INPUT VALUE (V)Figure 5. Warm-Up Drift Figure 8. Input Bias Current vs. Differential Input Voltage
Rev. E | Page 7 of 16
OP07
4VS = ±15V1000RS1 = RS2= 200k?THERMAL NOISE SOURCERESISTORS INCLUDEDEXCLUDED100
INPUT
BIAS
CURRENT
(nA)3OP07C2INPUT
NOISE
VOLTAGE
(nV/
Hz)10RS = 01OP07EVS = ±15VTA = 25°C00316-009–50–255110100FREQUENCY (Hz)1000TEMPERATURE (°C)Figure 9. Input Bias Current vs. Temperature
2.5VS = ±15V2.010Figure 12. Total Input Noise Voltage vs. Frequency
VS = ±15VTA = 25°CINPUT
OFFSET
CURRENT
(nA)1.5RMS
NOISE
(?V)11.0OP07C0.5OP07E00316-010–75–50–25k10kBANDWIDTH (Hz)100kTEMPERATURE (°C)Figure 10. Input Offset Current vs. Temperature
130Figure 13. Input Wideband Noise vs. Bandwidth,
0.1 Hz to Frequency Indicated
REFERRED TO INPUT5mV/CM AT OUTPUT120110VOLTAGE
(200nV/DIV)OP07CCMRR
(dB)101001k10k100kFREQUENCY (Hz)TIME (1s/DIV)00316-011Figure 11. Low Frequency Noise
Figure 14. CMRR vs. Frequency
Rev. E | Page 8 of 16
0-0130–1000.110000316-0120–751
120TA = 25°C110OP07C100PSRR
(dB)CLOSED-LOOP
GAIN
(dB)OP07100VS = ±15VTA = 25°C800.140200001k10k1001k10k100k1M10MFREQUENCY (Hz)FREQUENCY (Hz)Figure 15. PSRR vs. Frequency
1000TA = 25°CFigure 18. Closed-Loop Frequency Response for Various Gain Configurations
2824PEAK-TO-PEAK
AMPLITUDE
(V)VS = ±15VTA = 25°C800OPEN-LOOP
GAIN
(V/mV)2020000316-0160±5±10±15±2010k100kFREQUENCY (Hz)1MPOWER SUPPLY VOLTAGE (V)Figure 16. Open-Loop Gain vs. Power Supply Voltage
120–20–400.10100MAXIMUM
OUTPUT
(V)Figure 19. Maximum Output Swing vs. Frequency
20VS = ±15VVIN = ±10mVTA = 25°C15POSITIVE SWINGNEGATIVE SWING10VS = ±15VTA = 25°COPEN-LOOP
GAIN
(dB)5001k10k100k1M10M1kLOAD RESISTANCE TO GROUND (?)10kFREQUENCY (Hz)Figure 17. Open-Loop Frequency Response Figure 20. Maximum Output Voltage vs. Load Resistance
Rev. E | Page 9 of 16
0-019001k00316-018–2010
OP07
1000ABSOLUTE
VALUE
OF
OFFSET
VOLTAGE
(?V)
30.0TA = 25°CVOS TRIMMED TO < 5?V AT 25°CNULLING POT = 20k?22.5OP07C15.0OP07COP07E7.5OP07EPOWER
CONSUMPTION
(mW)060–75–50–25TOTAL SUPPLY VOLTAGE, V+ TO V– (V)TEMPERATURE (°C)Figure 21. Power Consumption vs. Power Supply
35OUTPUT
SHORT-CIRCUIT
CURRENT
(mA)VS = ±15VTA = 25°CTOTAL
DRIFT
WITH
TIME
(?V)Figure 24. Trimmed Offset Voltage vs. Temperature
1612840–4–8–120.3?V/MONTHTREND LINE0.3?V/MONTHTREND LINE0.3?V/MONTHTREND LINE0.2?V/MONTHTREND LINE0.2?V/MONTHTREND LINE3025VIN (PIN 3) = +10mV, VO = –15V0.2?V/MONTHTREND LINE20VIN (PIN 3) = –10mV, VO = +15V01112TIME FROM OUTPUT BEING SHORTED (Minutes)TIME (Months)Figure 22. Output Short-Circuit Current vs. Time
85.00ABSOLUTE
VALUE
OF
OFFSET
VOLTAGE
(?V)Figure 25. Offset Voltage Drift vs. Time
VS = ±15VRS = 100?OP07C63.7542.50OP07E21.25–50–255TEMPERATURE (°C)00316-0230–75
Figure 23. Untrimmed Offset Voltage vs. Temperature
Rev. E | Page 10 of 16
00316-02515–1600316-02410–100
OP07RFTYPICAL APPLICATIONS
EINR1SUM MODEBIASR310k?R410k?R510k?V+V+7V+V+27R33k?2–AD7115 ORAD85106EOEIN±10V–R110k?R527FD333D127––6OP07C610k?3+3A14+100kR2?4V–V–EO = –EINRFR1–IBRFFigure 26. Typical Offset Voltage Test Circuit
R410k?R1E10k?1+15VR2E10k?227–R310k?OP07C6E3EO3+R52.5k?4720-6–15V1300Figure 27. Typical Low Frequency Noise Circuit
20k?–1V+2–87INPUTOP076OUT+3+4820-6V–1300
Figure 28. Optional Offset Nulling Circuit
OP076OP07EO30V TO +10V3++FD33344D26V–209-26V–0-110kR2?3R1R26010R3=R4300Figure 29. Absolute Value Circuit
RFER1INSUM MODEBIASV+V+3kR3?27–27–R1OP07C6EOOP07C610k?3A2+3A14+100kR2?4V–V–EO = –EINRFR1+ IBRF03NOTES0-61. PINOUT SHOWN FOR P PACKAGE1300Figure 30. High Speed, Low VOS Composite Amplifier
R410k?R1E10k?1+15VR210k?27E2–R310k?6E3OP07EO3+R52.5k?4–15V13NOTES0-61. PINOUT SHOWN FOR P PACKAGE1300Figure 31. Adjustment-Free Precision Summing Amplifier
Rev. E | Page 11 of 16
OP07
R1R3
APPLICATIONS INFORMATION
The OP07 provides stable operation with load capacitance of up
to 500 pF and ±10 V swings; larger capacitances should be
decoupled with a 50 Ω decoupling resistor.
6EOSENDINGJUNCTIONV+27–REFERENCEJUNCTIONOP07R2R43+4V–R1R2=R3R4-032Stray thermoelectric voltages generated by dissimilar metals at
the contacts to the input terminals can degrade drift
performance. Therefore, best operation is obtained when both
input contacts are maintained at the same temperature,
preferably close to the package temperature.
NOTES61. PINOUT SHOWN FOR P PACKAGE1300Figure 32. High Stability Thermocouple Amplifier
10kR3?10kR4?10kR5?V+V+R1FD33327EIN10k?27D1–±10V–6OP076OP07EOA1A230V TO +10V3++FD33344D2V–V–10kR2?VA33NOTES0-61. PINOUT SHOWN FOR P PACKAGE1300Figure 33. Precision Absolute-Value Circuit
Rev. E | Page 12 of 16
OP07OUTLINE DIMENSIONS
5.00(0.1968)4.80(0.1890)4.00 (0.1574)3.80 (0.1497)81546.20 (0.2440)5.80 (0.2284)1.27 (0.0500)0.50 (0.0196)BSC1.75 (0.0688)0.25 (0.0099)45°0.25 (0.0098)1.35 (0.0532)8°0.10 (0.0040)0°COPLANARITY0.51 (0.0201)0.10SEATING0.31 (0.0122)0.25 (0.0098)1.27 (0.0500)PLANE0.17 (0.0067)0.40 (0.0157)COMPLIANTTO JEDEC STANDARDS MS-012-AACONTROLLING DIMENSIONSARE IN MILLIMETERS; INCH DIMENSIONSA-(INPARENTHESES)ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR605REFERENCE ONLYANDARE NOTAPPROPRIATE FOR USE IN DESIGN.060
Figure 34. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body S-Suffix
(R-8)
Dimensions shown in millimeters and (inches)
0.400 (10.16)0.365 (9.27)0.355 (9.02)850.280 (7.11)0.250 (6.35)140.240 (6.10)0.325 (8.26)0.310 (7.87)0.100 (2.54)0.300 (7.62)BSC0.060 (1.52)0.210 (5.33)MAX0.195 (4.95)MAX0.130 (3.30)0.115 (2.92)0.150 (3.81)0.015(0.38)0.015 (0.38)0.130 (3.30)MINGAUGE0.115 (2.92)SEATINGPLANE0.014 (0.36)PLANE0.010 (0.25)0.022 (0.56)0.018 (0.46)0.005 (0.13)0.430 (10.92)0.008 (0.20)MAX0.014 (0.36)MIN0.070 (1.78)0.060 (1.52)0.045 (1.14)COMPLIANTTO JEDEC STANDARDS MS-001CONTROLLING DIMENSIONSARE IN INCHES; MILLIMETER DIMENSIONS(INPARENTHESES)ARE ROUNDED-OFF INCH EQUIVALENTS FORREFERENCE ONLYANDARE NOTAPPROPRIATE FOR USE IN LEADS MAY BE CONFIGUREDAS WHOLE OR HALF 35. 8-Lead Plastic Dual-in-Line Package [PDIP]
P-Suffix
(N-8)
Dimensions shown in inches and (millimeters)
Rev. E | Page 13 of 16
A-606070
OP07
Package Option
N-8 (P-Suffix)
N-8 (P-Suffix)
N-8 (P-Suffix)
N-8 (P-Suffix)
R-8 (S-Suffix)
R-8 (S-Suffix)
R-8 (S-Suffix)
R-8 (S-Suffix)
ORDERING GUIDE
odel Temperature Range Package Description
OP07EP 0°C to 70°C 8-Lead PDIP
OP07EPZ1 0°C to 70°C 8-Lead PDIP
OP07CP 0°C to 70°C 8-Lead PDIP
OP07CPZ18-Lead PDIP
?40°C to +85°C
OP07CS 8-Lead SOIC_N
?40°C to +85°C
1OP07CSZ8-Lead SOIC_N
?40°C to +85°C
OP07CSZ-REEL18-Lead SOIC_N
?40°C to +85°C
OP07CSZ-REEL718-Lead SOIC_N
?40°C to +85°C
1 Z = RoHS Compliant Part.
Rev. E | Page 14 of 16
OP07NOTES
Rev. E | Page 15 of 16
OP07
NOTES
?2006-2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00316-0-7/09(E)
Rev. E | Page 16 of 16
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