2023年12月11日发(作者：二手捷豹xj价格)

8Gb: x4, x8, x16 DDR4 SDRAMFine Granularity Refresh ModeChanging Refresh RateIf the refresh rate is changed by either MRS or OTF. New

tREFI and

tRFC parameters willbe applied from the moment of the rate change. When the REF1x command is issued tothe DRAM,

tREF1 and

tRFC1 are applied from the time that the command was issued;when the REF2x command is issued,

tREF2 and

tRFC2 should be 89: OTF REFRESH Command TimingCK_cCK_tCommandDESREF1DESDEStRFC1 (MIN)tREFI1DESValidValidREF2DESDESValidDESREF2DEStRFC2 (MIN)tREFI2Don’t CareThe following conditions must be satisfied before the refresh rate can be changed. Oth-erwise, data retention cannot be guaranteed.?In the fixed 2x refresh rate mode or the OTF 1x/2x refresh mode, an even number ofREF2x commands must be issued because the last change of the refresh rate modewith an MRS command before the refresh rate can be changed by another MRS com-mand.?In the OTF1x/2x refresh rate mode, an even number of REF2x commands must be is-sued between any two REF1x commands.?In the fixed 4x refresh rate mode or the OTF 1x/4x refresh mode, a multiple-of-fournumber of REF4x commands must be issued because the last change of the refreshrate with an MRS command before the refresh rate can be changed by another MRScommand.?In the OTF1x/4x refresh rate mode, a multiple-of-four number of REF4x commandsmust be issued between any two REF1x are no special restrictions for the fixed 1x refresh rate mode. Switching betweenfixed and OTF modes keeping the same rate is not regarded as a refresh rate with TCR ModeIf the temperature controlled refresh mode is enabled, only the normal mode (fixed 1xmode, MR3[8:6] = 000) is allowed. If any other refresh mode than the normal mode isselected, the temperature controlled refresh mode must be Refresh Entry and ExitThe device can enter self refresh mode anytime in 1x, 2x, and 4x mode without any re-striction on the number of REFRESH commands that have been issued during themode before the self refresh entry. However, upon self refresh exit, extra REFRESH com-mand(s) may be required, depending on the condition of the self refresh conditions and requirements for the extra REFRESH command(s) are defined asfollows:?In the fixed 2x refresh rate mode or the enable-OTF 1x/2x refresh rate mode, it is rec-ommended there be an even number of REF2x commands before entry into self re-fresh after the last self refresh exit, REF1x command, or MRS command that set the8Gb: x4, x8, x16 DDR4 SDRAMREAD 8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READcommands at T0 and WRITE commands at operating in 2tCK WRITE preamble mode, CWL may need to be programmed to avalue at least 1 clock greater than the lowest CWL parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,Write CRC = 145: READ (BC4) OTF to WRITE (BC4) OTF with 1tCK Preamble in Same or Different BankGroupT0CK_cCK_tT1T5T6T7T8T9T10T11T12T13T14T15T16T17T18T19T20CommandREADDESDESWRITEDESDESDESDESDESDESDESDESDESDESDESDESDEStWRtWTRDESREAD to WRITE command delay= RL +BL/2 - WL + 2

tCKBank GroupAddressBGaBGa orBGb4 ClocksAddressBankCol nBankCol btRPREtRPSTtWPREtWPSTDQS_t,DQS_cRL = 11DQDOnDOn + 1DOn + 2DOn + 3DIbDIb + 1DIb + 2DIb + 3WL = 9Time Break Transitioning DataDon’t CareNotes: = 4, RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK, WL = 9 (CWL = 9, AL = 0),WRITE preamble = n = data-out from column n; DI b = data-in from column commands are shown for ease of illustration; other commands may be valid atthese 4 (OTF) setting activated by MR0[1:0] = 01 and A12 = 0 during READ commands at T0and WRITE commands at parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,Write CRC = Disable.8Gb: x4, x8, x16 DDR4 SDRAMCurrent Specifications – Patterns and Test ConditionsTable 146: IDD7 Measurement – Loop Pattern1A[17,13,11]]RAS_n/A16CAS_n/A15CK_t,

CK_cCommandWE_n/A14Sub-LoopA12/BC_nA[10]/APBG[1:0]2CycleNumberBA[1:0]ACT_nA[9:7]A[6:3]A[2:0]000000–––ACTRDADD_nACTRDA000F00–Repeat 3 until nRRD - 1, if nRRD > 4. Truncate if Repeat 3 until 2 × nRRD - 1, if nRRD > 4. Truncate if necessaryRepeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 insteadRepeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 3 insteadRepeat 3 until nFAW - 1, if nFAW > 4 × nRRD. Truncate if necessaryRepeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 insteadRepeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 2 insteadRepeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 insteadRepeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 0 insteadRepeat sub-loop 4Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 insteadRepeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 1 insteadRepeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 insteadRepeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 3 insteadRepeat sub-loop 4Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 insteadRepeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 2 insteadRepeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 insteadRepeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 0 insteadRepeat sub-loop 4Repeat 3 until nRC - 1, if nRC > 4 × nFAW. Truncate if _t, DQS_c are 1 is a \"Don\'t Care\" for x16 signals are VDDQ except when burst sequence drives each DQ signal by a READ com-mand.234567Static

HighToggling89 × nRRD3 × nRRD4 × nRRDnFAWnFAW + nRRDnFAW + 2 × nRRDnFAW + 3 × nRRDnFAW + 4 × nRRD2 × nFAW2 × nFAW + nRRD2 × nFAW + 2 ×nRRD2 × nFAW + 3 ×nRRD2 × nFAW + 4 ×nRRD3 × nFAW3 × nFAW + nRRD3 × nFAW + 2 ×nRRD3 × nFAW + 3 ×nRRD3 × nFAW + 4 ×nRRD4 × nFAWNotes:

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